Memory devices conventionally include arrays of bit cells that each store a bit of data. Each data bit can represent a logical low (“0”) or a logical high (“1”), which may correspond to a state of the bit cell. For example, during a read operation a voltage level at a selected bit cell close to ground may be representative a logical low or “0” and a higher voltage level may be representative of a logical high or “1.” Bit lines are coupled to various bit cells in the memory array and couple the bit cells to other components used in read/write operations.
For example, during a read operation, the voltage/current representing a state of a selected bit cell may be detected via the bit lines coupled to the selected bit cell. A sense amplifier may be coupled to the bit lines to amplify the differential voltage/current to aid in determining the logical state of the bit cell.
As discussed above, a sense amplifier (SA) is a basic component that is used for operations in memory devices. A commonly used sense amplifier is a current latched sense amplifier (CLSA).
FIG. 1 illustrates a conventional CLSA 100. Referring to FIG. 1, the CLSA 100 includes NMOS transistors N1 through N5, PMOS transistors P1 through P4 and capacitors C1 and C2. The CLSA 100 receives differential input bit line BIT and inverted bit line BITB, sense signal SENSE and is coupled to a power supply voltage Vdd.
Referring to FIG. 1, the differential inputs BIT, BITB are applied to gates of NMOS transistors N1 and N2, respectively. The sense signal SENSE is applied to NMOS transistor N5 and PMOS transistors P1 and P4. When the sense signal SENSE is low, transistors P1 and P4 are conducting or “on” and allow capacitors C1 and C2 to charge. When the sense signal SENSE transitions to a higher logic level (e.g., “1”), the current through the gates N1 and N2 will be different if the voltages on differential inputs BIT and BITB are different. A different current flow through N1/N3 and N2/N4 will cause a voltage difference between output nodes sout and soutb as the capacitors will be discharged at a different rate. If a voltage on one of the output nodes (sout or soutb) reaches a threshold value to turn on one of cross coupled transistors P2 or P3, and turn off one of corresponding transistors N3 or N4, then a corresponding one of nodes sout or soutb will be coupled to Vdd. The other pair of transistors P1/N3 or P2/N4 cross coupled to the output node (sout or soutb) and coupled to Vdd will remain in a state with the PMOS transistor off and the NMOS transistor conducting. Accordingly, one of the output nodes sout or soutb will be latched to a high state and the other output node will be discharged, so the voltage differential between sout and soutb will be further amplified.
FIG. 2 illustrates another conventional CLSA 200. Referring to FIG. 2, the CLSA 200 includes NMOS transistors N1 through N5, PMOS transistors P1 through P6 and capacitors C1 and C2. The CLSA 200 receives differential inputs BIT and BITB, sense signal SENSE and is coupled to power supply voltage Vdd. The operation of the CLSA 200 is similar to that of the CLSA 100. However, the CLSA 200 differs from CLSA 100 in that the differential inputs BIT and BITB are coupled to nodes sa and sab through PMOS transistors P5 and P6 (which are not present in CLSA 100) prior to a triggering of a sensing operation (when sense signal SENSE is low), which can increase a sensitivity of the CLSA 200 as compared to CLSA 100.
Thus, CLSA 100 and CLSA 200 are configured to sense voltage differentials in different manners. Also, CLSA 200 is able to achieve greater sensitivity than the CLSA 100 but only at the cost of including additional PMOS transistors, which can increase the layout area, power consumption and leakage of the sense amplifier.